This is another follow-up question to Combinatorial synthesis: Better technology mapping results.
This is my Yosys TCL control script:
yosys -import
set libfile osu018_stdcells.lib
read_liberty -lib $libfile
read_verilog test.v
hierarchy;
procs; opt
memory; opt
fsm -norecode; opt -full
techmap; opt -full
dfflibmap -liberty $libfile
abc -liberty $libfile \
-script {+strash;ifraig;scorr;dc2;dretime;strash;&get,-n;&dch,-f;&nf,{D};&put}
clean
write_verilog test_synth.v
The osu018_stdcells.lib file used is part of the Qflow version 1.1 package.
This is the test.v file:
module test (
input rx_clk,
input rxena,
input rstn,
input [2:0] d,
output reg [2:0] q
);
wire rx_rstn = rstn & rxena;
always @ (negedge rx_clk or negedge rx_rstn) begin
if (!rx_rstn) begin
q <= 0;
end else begin
q <= d;
end
end
endmodule
Yosys (version 0.5+ (git sha1 f13e387, gcc 5.3.1-8ubuntu2 -O2 -fstack-protector-strong -fPIC -Os)) produces the following test_synth.v output netlist:
/* Generated by Yosys 0.5+ (git sha1 f13e387, gcc 5.3.1-8ubuntu2 -O2 -fstack-protector-strong -fPIC -Os) */
(* src = "test.v:1" *)
module test(rx_clk, rxena, rstn, d, q);
wire _0_;
wire _1_;
wire _2_;
(* src = "test.v:5" *)
input [2:0] d;
(* src = "test.v:6" *)
output [2:0] q;
(* src = "test.v:4" *)
input rstn;
(* src = "test.v:2" *)
input rx_clk;
(* src = "test.v:8" *)
wire rx_rstn;
(* src = "test.v:3" *)
input rxena;
INVX1 _3_ (
.A(rx_clk),
.Y(_0_)
);
AND2X1 _4_ (
.A(rstn),
.B(rxena),
.Y(rx_rstn)
);
INVX1 _5_ (
.A(rx_clk),
.Y(_1_)
);
INVX1 _6_ (
.A(rx_clk),
.Y(_2_)
);
DFFSR _7_ (
.CLK(_1_),
.D(d[0]),
.Q(q[0]),
.R(rx_rstn),
.S(1'b1)
);
DFFSR _8_ (
.CLK(_2_),
.D(d[1]),
.Q(q[1]),
.R(rx_rstn),
.S(1'b1)
);
DFFSR _9_ (
.CLK(_0_),
.D(d[2]),
.Q(q[2]),
.R(rx_rstn),
.S(1'b1)
);
endmodule
Obviously, there are 3 instances of the INVX1 cell, one for each of the three flip-flops in this design. I would have expected only one of these inverters and its driven net shared between the flip-flop CLK inputs.
In another design (with about 30 registers that are triggered off the falling clock edge), I have seen just one inverter but its output goes through one buffer per flip-flop, which is also not ideal.
Is there a way to get Yosys to combine/share these resources among the registers?
Is there a way to get Yosys to combine/share these resources among the registers?
Simply run opt_merge after running dfflibmap.