Verilog Arithmetic and Logic Unit (ALU) Compilation Error

Question

I am getting a compilation error as such:

Error (10663): Verilog HDL Port Connection error at jdb_Blogic_v.v(7): output or inout port "f" must be connected to a structural net expression

I commented the line with the error. How do I fix it?

I also included the mux2to1 function code.

module jdb_Blogic_v (FS2_in, FS1_in, B_in, Y_out);

input FS2_in, FS1_in;
input [3:0] B_in;
output reg [3:0] Y_out;

jdb_mux2to1_v stage0 (B_in[0], FS1_in, FS2_in, Y_out[0]); //ERROR IS HERE ACCORDING TO COMPILER
jdb_mux2to1_v stage1 (B_in[1], FS1_in, FS2_in, Y_out[1]);
jdb_mux2to1_v stage2 (B_in[2], FS1_in, FS2_in, Y_out[2]);
jdb_mux2to1_v stage3 (B_in[3], FS1_in, FS2_in, Y_out[3]);

endmodule



module jdb_mux2to1_v (s, x1, x2, f);

input x1, x2, s;
output f;
wire    k, g, h;

not (k, s);
and (g, k, x1);
and (h, s, x2);
or (f, g, h);

endmodule

Answer 1

Change the declaration of Y_out from output reg [3:0] to just output [3:0]. This will change it from being a reg to a wire.

A reg can only be assigned to from within a procedural statement, such as an always block.