Gcc Make: No rule to make target. Why?

Question

I have this makefile.

IDIR=-I../inc/pvt -I../inc/pub
CC=gcc
CFLAGS=-I$(IDIR)

ODIR=obj
LDIR =../lib

_DEPS = teos_config.h teos_linkedlist.h teos_error.h teos_event.h teos_task.h
DEPS = $(patsubst %,$(IDIR)/%,$(_DEPS))

_OBJ = teos_event.o teos_init.o teos_linkedlist.o teos_log.o teos_main.o teos_mem.o teos_task.o
OBJ = $(patsubst %,$(ODIR)/%,$(_OBJ))

$(ODIR)/%.o: %.c $(DEPS)
    $(CC) -c -o $@ $< $(CFLAGS)

teosmake: $(OBJ)
    gcc -o $@ $^ $(CFLAGS)

Why is it giving me this error, and how may I fix it?

make -C src
make[1]: Entering directory 'C:/Users/<user>/git/teos/src'
make[1]: *** No rule to make target 'obj/teos_event.o', needed by 'teosmake'.  S
top.
make[1]: Leaving directory 'C:/Users/<user>/git/teos/src'
makefile:6: recipe for target 'teos_root' failed
make: *** [teos_root] Error 2

I'm running gcc version 4.9.3. Thanks.

Answer 1

That means that your pattern rule is not considered valid by make. Most likely it means that one of the prerequisites you've defined doesn't exist and can't be created.

If you run make with the -d flag it will tell you exactly what files it's looking for and which one(s) it couldn't find. Note that the output is voluminous so you should redirect it to a file to look at.

You should take the prerequisites out of the pattern rule and define them separately: this will give you a much better message:

$(ODIR)/%.o: %.c
        $(CC) -c -o $@ $< $(CFLAGS)

$(OBJ): $(DEPS)

Doing it this way the only thing you need for the pattern to match is that the source file exist. If one of the prerequisites doesn't match you'll get a specific error about that, since the dependency relationship is explicit rather than being inferred by the pattern matching.