VHDL constant array case choice

Question

I have the following declaration in my architecture:

architecture behavioral of my_widget is
    type register_bank_t is array(1 to 4) of std_logic_vector(31 downto 0); 
    -- register addresses
    constant address : register_bank_t := (
        x"0000_1081", -- 1 
        x"0000_1082", -- 2 
        x"0000_1083", -- 3 
        x"0000_1084"  -- 4 
    );
..

Then later, in a process inside the same architecture, I do:

case bus_addr is
    when address(1) =>
        r_output_value <= reg(1);
    when address(2) =>
        r_output_value <= reg(2);
    when address(3) =>
        r_output_value <= reg(3);
    when address(4) =>
        r_output_value <= reg(4);
    when others =>
        r_output_value <= (others => '0'); 
end case;

I can't figure out why Modelsim gives me the following warning:

(vcom-1937) Choice in CASE statement alternative must be locally static.

When all the choices are clearly constants at compile time.

Answer 1

Here is what I have found out. Hopefully it will help the next person searching for this answer:

The warning is caused by the fact that constants defined at architecture level are not considered locally static within the process by the compiler (pre VHDL-2008). In order for that to happen, they have to be defined inside the process's declaration block.

One solution is to compile with VHDL 2008 (-2008 option in vcom). Another option is to pass the nocasestaticerror option to vcom which will suppress the warning.