Can't make the required diagram

Question

This is the code for a 9-bit parity generator, but it is not giving the required RTL view in Quartus

Library IEEE;
use IEEE.std_logic_1164.all;

entity PG is
port (A,B,C,D,E,F,G,H,I : IN std_logic;
      Even : OUT std_logic );
end PG;

Architecture arch of PG is
    Signal J,K,L,M,N,O,P,Odd : std_logic ;
BEGIN
    J <= A xor B;
    K <= C xor D;
    L <= E xor F;
    M <= G xor H;
    N <= J xor K;
    O <= L xor M;
    P <= N xor O;
    Odd <= P xor I;
    Even <= not Odd;
END arch;

This is the required image that is required as output:

This is the output RTL image that I get:

Answer 1

It looks like the correct RTL view to me. Quartus has chosen to display the logic as one 9-input XOR gate instead of many 2-input XOR gates. The boolean behaviour of both is identical. There is no ODD output, because ODD is a signal not an output.