Why is this MUX with const. inputs not optimised away?

Question

This is a follow-up question to Combinatorial synthesis: Better technology mapping results.

I am using Yosys (version 0.5+ (git sha1 f13e387, gcc 5.3.1-8ubuntu2 -O2 -fstack-protector-strong -fPIC -Os)) with the following synthesis script:

read_liberty -lib  my_library.lib
read_verilog test.v
hierarchy -check -top test
proc; opt; memory; opt; fsm -norecode; opt
techmap; opt
dfflibmap -liberty my_library.lib
abc -liberty my_library.lib -script \
    +strash;ifraig;scorr;dc2;dretime;strash;&get,-n;&dch,-f;&nf,{D};&put
hilomap -hicell LIB_TIEHI Y -locell LIB_TIELO Y
clean
write_verilog -noattr -noexpr output.v
stat

...to synthesise the following Verilog code (test.v):

module mux4(
    input  i0, i1, i2, i3,
    input  s0, s1,
    output z);
  reg    zint;
  always @(*) begin
    case ({s1, s0})
      2'b00:   zint = i0;
      2'b01:   zint = i1;   
      2'b10:   zint = i2;   
      2'b11:   zint = i3;   
      default: zint = i3;
    endcase
  end
  assign z = zint;
endmodule

module test (
    input a,b,c,d,
    output result
  );
  mux4 inst (
    .i0(a), .i1(b), .i2(c), .i3(d), 
    .s0(1'b0), .s1(1'b0),           # constants here!
    .z(result)
  );
endmodule

The synthesis results include a LIB_MUX4 instance with both S0 and S1 tied low by two LIB_TIELO instances.

Why doesn't Yosys see that S0 and S1 are constant and reduce the output to something like this

module test(a, b, c, d, result);
  input a;
  input b;
  input c;
  input d;
  output result;
  assign result = a;
endmodule

instead?

I tried using the clean -purge, opt_muxtree and opt_clean commands, but without success - the static LIB_MUX instance is always in the resulting netlist.

Answer 1

1. You need to run flatten if you want optimization across hierarchical boundaries.

2. You probably want to run opt -full shortly before running techmap, but after running high-level optimizations like fsm and share.

3. JFYI: If you do not provide all files necessary to run your test case, people will not be able to reproduce what you are talking about. I don't have your my_library.lib, so I did not even bother trying to run your code.