Array implementation on FPGA using VHDL

I have following line in my VHDL code:

prbs_reg_feed <= prbs_reg_ip(byte_indx);

where

type reg_type is array (0 to 63) of std_logic_vector(8 downto 0);

signal prbs_reg_feed           : std_logic_vector(8 downto 0);

signal prbs_reg_ip             : reg_type;

I want know the FPGA implementation of this.

Thanks, Vijay

Solution

This will get synthesised to a lot of combinational logic. This combinational logic will have nearly 600 inputs and 9 outputs.

With an FPGA synthesier, if you were to write some code around this line:

prbs_reg_feed <= prbs_reg_ip(byte_indx);

to make your code behave more like a RAM, then you would probably get a RAM. (You should read the report files output by your synthesiser to make sure.)

  process(clock) is
  begin
    if rising_edge(clock) then
      if we = '1' then
        prbs_reg_ip(byte_indx) <= datain;
      end if;
     prbs_reg_feed <= prbs_reg_ip(byte_indx);
    end if;
  end process;

NB: this assumes byte_indx is an integer.