I'm having difficulty understanding the effects of this code: My component:
library IEEE;
use IEEE.std_logic_1164.all;
entity problem is
port(
clk : in std_logic;
a : in std_logic);
end problem;
architecture impl of problem is
signal a_sig : std_logic;
begin
clk_proc : process(clk)
begin
if rising_edge(clk) then
a_sig <= '0';
end if;
end process;
a_proc : process(a)
begin
report "a received : " & std_logic'image(a);
a_sig <= a;
end process;
a_sig_proc : process(a_sig)
begin
report "a_sig set : " & std_logic'image(a_sig);
end process;
end impl;
and this is my testbench.vhd:
library IEEE;
use IEEE.std_logic_1164.all;
entity testbench is
end testbench;
architecture tb of testbench is
component problem is
port ( clk : in std_logic;
a : in std_logic);
end component;
constant clk_period : time := 1 ms;
signal clk_sig : std_logic;
signal a_sig : std_logic;
begin
dut : problem port map (clk_sig, a_sig);
process
begin
clk_sig <= '1';
wait for clk_period/2;
clk_sig <= '0';
wait for clk_period/2;
end process;
process
begin
wait for clk_period * 0.75;
a_sig <= '1';
end process;
end tb;
and the result of running the code is as follows:
$ ghdl -r testbench --vcd=testbench.vcd --stop-time=2ms
problem.vhd:23:5:@0ms:(report note): a received : 'U'
problem.vhd:29:5:@0ms:(report note): a_sig set : 'U'
problem.vhd:23:5:@750us:(report note): a received : '1'
problem.vhd:29:5:@1ms:(report note): a_sig set : 'X'
./testbench:info: simulation stopped by --stop-time
I can understand the 'U' signals being received at 0ms, and I can understand the '1' signal being received in problem.a_proc at 750microseconds. The first thing that confuses me is, why isn't the problem.a_sig_proc being triggered by a_sig being set in the same process? And then, when problem.a_sig_proc is triggered, a_sig has the value of 'X'. If someone could point me to a ressource to explain this, it would be great :)
Thanks in advance!
You are driving the a_sig signal from multiple processes (clk_proc and a_proc). You will need to remove the assignment to a_sig in one of the processes (as the simulator cannot resolve which assignment takes precedence), or drive 'Z' (high impedence) onto a_sig from the processes, while it is not "their turn". There are good explanations here and here