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verilogsynthesisvivado

Verilog: Does Vivado Synthesis tool, add signals to sensitivity list automatically?

module Test( input i );
 (* MARK_DEBUG = "TRUE" *) reg b;

 always @(i)
 begin
      if(i)
           b = 1'h0;
      else
           b = ~b;
 end
endmodule

After synthesizing this code I get the following result during Post-Synthesis-Simulation process with ModelSim simulator :

** Error (suppressible): (vsim-3601) Iteration limit 10000000 reached at time 20 ns.

But I have no problem with Behavioral-Simulation phase.

It seems that the Vivado adds "b" signal to the sensitivity list automatically, Isn't it ?

Solution

  • Think about this module in terms of the hardware it implies.

    b can't be implemented as a register or latch, because it's being assigned to from a combinational always block. However, the resulting circuit contains a combinational loop which won't stabilize on any value when i is 0:

    schematic