Delay a signal in VHDL Testbench

I would like to put a delay on a signal in my testbench. The problem is that I need hundreds of clock cycles and thus I don't want to use hundreds of intermediate signals.

Since this is just for a simulation use, is there any way to add a delay with unsynthetisable code (perhaps with WAIT or AFTER)?

Solution

It sounds like you want to use a transport delay. By default, if you make a delayed assignment, this will use an 'inertial' delay model:

my_sig_delayed <= my_sig after 100 ns;

However, with this example, if your signal toggles more than once in 100 ns, your my_sig_delayed signal will not follow it as you might expect it to. By using a transport delay, you replicate a 'delay line'.

my_sig_delayed <= transport my_sig after 100 ns;

For a more detailed explanation, try this http://www.gmvhdl.com/delay.htm

An alternative would be to use a shift register with a length of whatever delay you need:

signal delay_line : std_logic_vector(255 downto 0) := (others => '0');

...

process (clk)
begin
  if (rising_edge(clk)) then
    delay_line <= delay_line(delay_line'left-1 downto 0) & my_sig;
  end if;
end process;

my_sig_delayed <= delay_line(delay_line'left);