SystemVerilog: Assignment pattern element <name>: Element widths don't match (error: vlog-7034)

Question

I'm trying (unsuccessfully) to use a multidimensional array to send hardcoded constant arrays that can be indexed by a counter in other modules.

My current strategy is to use parameter arrays, which compiles and deploys, but only the first bit in each array element is considered once on the hardware. This was reflected in the RTL view, so I went to modelsim and received this error:

Error: (vlog-7034) <path>(<line>): Array assignment to type 'reg[9:0] $[19:0]' from type 'reg $[19:0]':  Assignment pattern element 'NoMove':  Element widths (10, 1) don't match

My code is here:

module EScheduler(input Clk, Reset,
                output reg [9:0] ESchedCtr,
                output reg [9:0] ESchedX [NE - 1:0][NM - 1:0], ESchedY [NE - 1:0][NM - 1:0],
                output reg [9:0] EShipInitialX [NE - 1:0], EShipInitialY [NE - 1:0],
                output reg ESchedFire [NE - 1:0][NM - 1:0]);
    logic clkby2;
    initial clkby2 = 0;
    always_ff @ (posedge Clk)
    begin
        clkby2 <= ~clkby2;
    end
    parameter PlusOne = 10'b1;
    parameter MinusOne = (~(PlusOne) + 10'b1);
    parameter reg NoMove [NM - 1:0] = '{10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0,
                                        10'd0, 10'd0, 10'd0, 10'd0, 10'd0};
    parameter reg CircleX [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            PlusOne, PlusOne, PlusOne, PlusOne, PlusOne};
    parameter reg CircleY [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                            MinusOne, MinusOne, MinusOne, MinusOne, MinusOne};
    parameter reg BackAndForth [NM - 1:0] = '{  PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                                MinusOne, PlusOne, MinusOne, PlusOne, MinusOne,
                                                PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                                MinusOne, PlusOne, MinusOne, PlusOne, MinusOne};
    parameter reg FireOnFrame13 [NM - 1:0] = '{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                    1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                    1'b0, 1'b0, 1'b1, 1'b1, 1'b1,
                                    1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };
    always_ff @ (posedge clkby2)
    begin
        if(Reset == 1'b1)
        begin
            ESchedCtr <= 10'b0;
        end
        else
        begin
            if(ESchedCtr >= NM - 1)
                ESchedCtr <= 10'b0;
            else
                ESchedCtr <= ESchedCtr + 10'b1;
        end
        ESchedFire <= '{ FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13,
                FireOnFrame13, FireOnFrame13 };
    end
    always_comb
    begin
        EShipInitialX = '{10'd020, 10'd080, 10'd140, 10'd200, 10'd260, 10'd320, 10'd380, 10'd440, 10'd500, 10'd560};
        EShipInitialY = '{10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040, 10'd040};
        ESchedX = '{9: CircleX, 8: BackAndForth, 7: CircleY, 6: NoMove, 5: NoMove,
                    4: NoMove, 3: NoMove, 2: NoMove, 1: NoMove, 0: NoMove};
        ESchedY = '{CircleY, NoMove, CircleX, NoMove, NoMove,
                    NoMove, NoMove, NoMove, NoMove, NoMove};
    end
endmodule 

I started on using the answer provided here: https://verificationacademy.com/forums/systemverilog/working-multi-dimensional-associative-arrays

Which is to use a colon to define the indices at which each element resides, but this has been unsuccessful. No other mentions of this error come up in Google searches.

Answer 1

Silly mistake, fortunately. I forgot to include the field width in the parameter declaration:

parameter reg [9:0] CircleX [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        PlusOne, PlusOne, PlusOne, PlusOne, PlusOne};
parameter reg [9:0] CircleY [NM - 1:0] = '{   PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        PlusOne, PlusOne, PlusOne, PlusOne, PlusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne,
                                        MinusOne, MinusOne, MinusOne, MinusOne, MinusOne};
parameter reg [9:0] BackAndForth [NM - 1:0] = '{  PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                            MinusOne, PlusOne, MinusOne, PlusOne, MinusOne,
                                            PlusOne, MinusOne, PlusOne, MinusOne, PlusOne,
                                            MinusOne, PlusOne, MinusOne, PlusOne, MinusOne};
parameter reg FireOnFrame13 [NM - 1:0] = '{1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
                                1'b0, 1'b0, 1'b1, 1'b1, 1'b1,
                                1'b0, 1'b0, 1'b0, 1'b0, 1'b0 };

I'm going to leave this solution up so that others can benefit from seeing this error code in a search result.