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arraysfor-loopconstraintssystem-verilog-assertions

Constraint array of integers to be within certain range

All,

I'm trying to come up with a SystemVerilog constraint which will for e.g. byte my_array [0:8] loop through all the elements in the array to restrict their values to be within the range from 1 to 9. Something like:

restrict: assume property (
    foreach(my_array[i]) my_array[i] inside {[1:9]}
);

The above is not accepted by the parser. Please help! I can generate 9 constraints within a loop, but would like to have something more elegant. So, below is a current workaround.

genvar i;
 for (i=0; i<=8; i++) begin : legal_nums
  restrict: assume property (
   my_array[i] inside {[1:9]}
 ); 
end : c

Thanks!

Solution

  • Since you are writing properties, you need to use the generate statement. I did this a while ago and after much research, this was the only way possible.