Numbers of no-ops betweeen MIPS instructions

Question

I have a sequence of instructions as follows:

I1 lw  $1, 40($6)
I2 add $6, $2, $2
I3 sw  $6, 50($1)

The question is:

In a basic five-stage pipeline without forwarding, how many noops should be there between I2 and I3?

I think the number is 2, while the solution given by the book is 1. Do I miss something? Any clues are appreciated.

The question actually is the Exercise 4.13 of Computer Organization and design, The Hardware/Software Interface Fourth editon.

Answer 1

Well, if you don't have forwarding in your pipeline, the only way of solving this conflict is with two noops.

    1    2    3    4    5    6    7    8    9
I1  IF   ID   EX   MEM  WB
I2       IF   ID   EX   MEM  [WB]
NOP           IF   ID   EX   MEM  WB
NOP                IF   ID   EX   MEM  WB
I3                      IF   [ID] EX   MEM  WB

You can clearly see from this rough table that Write Back of I2 and Instruction Decode of I3 are only "aligned" with two noops. I assume your textbook is wrong.