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vectorvhdl

VHDL Vector passing

I want to pass a value from one vector to another. Can I simply do it this way?

vector_one : out STD_LOGIC_VECTOR (3 downto 0);
vector_two : out STD_LOGIC_VECTOR (3 downto 0);

vector_one <= vector_two;
Solution

  • The vector_one is an output port (mode out), and reading this is allowed in VHDL-2008, so you can do:

    vector_one <= vector_two;

    However, in VHDL-2002 it is not allowed to read an output port, so you must drive both outputz from the source, say vector_source, like:

    vector_one <= vector_source;
vector_two <= vector_source;

    Generally, it should be avoided to duplicate an output signal like that, since it is not obvious from the use of that module that some output are driven with identical values, which makes it harder to understand the module use.