I want to design an 8 bit alu in VHDL but I get this errors, I think it has something to do with the fact that my inputs are declared as bit_vectors. Is that true?
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(19): No feasible entries for infix operator "+".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(19): Type error resolving infix expression "+" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(21): No feasible entries for infix operator "-".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(21): Type error resolving infix expression "-" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(23): No feasible entries for infix operator "-".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(23): Type error resolving infix expression "-" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(25): No feasible entries for infix operator "+".
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(25): Type error resolving infix expression "+" as type std.STANDARD.BIT_VECTOR.
** Error: C:/Programs/Modeltech_pe_edu_10.4a/examples/alu.vhdl(40): VHDL Compiler exiting
This is my module:
entity alu is
port ( bus_a : in bit_vector(7 downto 0);
bus_b : in bit_vector(7 downto 0);
state : in bit_vector (2 downto 0);
out_c : out bit_vector(7 downto 0));
end alu;
architecture behave of alu is
begin
process(bus_a, bus_b, state)
begin
case state is
when "000" =>
out_c<= bus_a + bus_b; --addition
when "001" =>
out_c<= bus_a - bus_b; --subtraction
when "010" =>
out_c<= bus_a - 1; --sub 1
when "011" =>
out_c<= bus_a + 1; --add 1
when "100" =>
out_c<= bus_a and bus_b; --AND gate
when "101" =>
out_c<= bus_a or bus_b; --OR gate
when "110" =>
out_c<= not bus_a ; --NOT gate
when "111" =>
out_c<= bus_a xor bus_b; --XOR gate
when others =>
NULL;
end case;
end process;
end architecture behave;
Do you have any ideas why and maybe you have any other suggestions for the problem? Thanks in advance!
A bit_vector is just a collection of bits, but without any intrinsic value, so you have to tell VHDL how to understand the bit_vector as a value before it makes sense to use an arithmetic operator like addition (+).
Take a look a the numeric_bit package, which has the types signed and unsigned as array of bit, whereby you can specify that a bit_vector is to be considered as an either signed or unsigned value when doing addition.
So the library use and convert can look like below for unsigned addition:
library ieee;
use ieee.numeric_bit.all;
...
out_c <= bit_vector(unsigned(bus_a) + unsigned(bus_b)); --addition
But usually the std_logic_vector is used instead of the bit_vector, so you may consider looking at the std_logic_1164 and numeric_std packages instead.