vhdlfixed-pointvivadotest-bench
Show a fixed point value in vivado
Let's say I have a fixed point value in my VHDL - Code which is defined as std_logic_vector. I know that my last 4-bit are the decimals.
When I use the simulator it will of course not see the last 4 bits as decimals, is there any possibility to change it in the simulation, so that the simulation knows that the 3rd bit has the value of 0.5 , the 2nd the value of 0.25 and so on ?
Solution
It's possible in Vivado to show the result in the simulator as a fixed point representation.
When you rightclick in the simulator on the signal you want to show in fixed point, click radix --> real settings. There you get the following window and you can select fixed point.
