Someone can check this code and tell me where's the mistake? The compiler send this error message: Funcio_2.vhd(10): near "OR": (vcom-1576) expecting ')'.
--Definimos la entidad funcio_2-
ENTITY funcio_2 IS
PORT(a,b,c,d:IN BIT;f:OUT BIT);
END funcio_2;
--Definimos su arquitectura logica-
ARCHITECTURE logica OF funcio_2 IS
BEGIN
f<= (((NOT a) AND b) AND ((NOT c) OR b) AND(NOT d) OR(a AND c AND d) OR a AND(NOT d)) AND (NOT(a OR (NOT d)) OR NOT(((NOT a) AND b) AND ((NOT c) OR b) AND(NOT d) OR(a AND c AND d) OR a AND(NOT d)) AND (a OR (NOT d));
END logica;
Rewrited my code and now looks like:
f<= (NOT a AND b AND NOT c OR b AND NOT d OR a AND c AND d OR a AND NOT d) AND NOT(a OR (NOT d)) OR NOT(NOT a AND b AND NOT c OR b AND NOT d OR a AND c AND d OR a AND NOT d) AND (a OR (NOT d));
Isn't working
From what I can tell, Modelsim requires expressions combining AND and OR operators to be parenthesized to disambiguate their precedence. I couldn't find this documented anywhere so I just made an educated guess and it turned out to compile. According to the VHDL standard, AND and OR have the same precedence, so they should be evaluated left-to-right.
I took the liberty of defining some temporary signals, but I think this is the same thing:
t1 <= ((((((NOT a AND b AND NOT c) OR b) AND NOT d) OR a) AND c AND d) OR a) AND NOT d;
t2 <= a OR (NOT d);
t3 <= t1 AND NOT t2;
t4 <= t3 OR NOT t1;
f <= t4 AND t2;
If you wanted AND to bind more tightly than OR, like in some other languages, then the VHDL would never have done what you wanted anyway and Modelsim just caught the bug. Either way you have to parenthesize the expression to clarify what you want.
Of course, you could also do some Boolean algebra:
f <= a XNOR d;