I am implementing a MIPS Instruction decoder, but in the wave, I see all the assign logic variables like jump, immediate_i,regWrite etc as xxx, although I have initialized them as follows. Even if I assume that, for eg., in jump, J is X, shoudn't it still go to 0 and not x?
assign immediate_i = (opcode == (ADDI || ANDI || SLTI || XORI || LW || SW )) ? 1'b1 : 1'b0;
assign memRead = LW ? 1'b1:1'b0;
assign memtoReg = LW ? 1'b1:1'b0 ;
assign memWrite = SW ? 1'b1:1'b0;
assign jump = J ? 1'b1:1'b0;
assign jumpReg = JR ? 1'b1:1'b0;
assign bgtz = BGTZ ? 1'b1:1'b0;
module Instr_decode (
input logic signed [31:0] instr,
output logic regDest,
output logic jump,
output logic branch,
output logic bgtz,
output logic memtoReg,
output logic memRead,
output logic memWrite,
output logic regWrite,
output logic [8:0] ALU_control,
output logic signed [31:0] imm_data_extended,
output logic target,
output logic immediate_i,
output logic [4:0] shamt,
output logic jumpReg
);
logic [5:0] opcode;
logic [4:0] rs;
logic [4:0] rt;
logic [4:0] rd;
logic [5:0] func;
logic signed [15:0] immediate_data;
logic signExtend_i;
logic [4:0] wr_reg_addr; //for RF
logic ADD;
logic ADDI;
logic AND;
logic ANDI;
logic BEQ;
logic BGTZ;
logic BNE;
logic J ;
logic JR ;
logic LW ;
logic NOR;
logic OR ;
logic ORI;
logic SLT;
logic SLTI;
logic SRA;
logic SUB;
logic SW ;
logic XOR;
logic XORI;
//Extracting the fields of Instruction bits
assign opcode = instr[31:26];
assign shamt = instr[10:6];
assign func = instr[5:0];
assign target = instr[25:0];
assign immediate_data = immediate_i ? instr[15:0] : 16'dz;
assign rs = instr[25:21];
assign rt = instr[20:16];
assign rd = instr[15:11];
//assigning the decoder outputs
assign immediate_i = (opcode == (ADDI || ANDI || SLTI || XORI || LW || SW )) ? 1'b1 : 1'b0;
assign memRead = LW ? 1'b1:1'b0;
assign memtoReg = LW ? 1'b1:1'b0 ;
assign memWrite = SW ? 1'b1:1'b0;
assign jump = J ? 1'b1:1'b0;
assign jumpReg = JR ? 1'b1:1'b0;
assign bgtz = BGTZ ? 1'b1:1'b0;
assign regWrite = (ADD | ADDI | AND | ANDI | SUB | OR | XOR | NOR | SLT | SLTI | LW | SRA | ORI | XORI) ? 1'b1:1'b0 ;
assign branch = (BEQ | BNE) ? 1'b1:1'b0;
assign regDest = (ADDI | ANDI | LW | SW | SLTI | XORI) ? 1'b1:1'b0;
//ALU Control logic output
assign ALU_control[0] = (ADD | ADDI | LW | SW) ? 1'b1 : 1'b0;
assign ALU_control[1] = (AND | ANDI) ? 1'b1:1'b0;
assign ALU_control[2] = NOR ? 1'b1:1'b0;
assign ALU_control[3] = OR ? 1'b1:1'b0;
assign ALU_control[4] = (SLT | SLTI) ? 1'b1:1'b0;
assign ALU_control[5] = SRA ? 1'b1:1'b0;
assign ALU_control[6] = (SUB | BEQ) ? 1'b1:1'b0 ;
assign ALU_control[7] = BNE ? 1'b1:1'b0 ;
assign ALU_control[8] = (XOR | XORI) ? 1'b1:1'b0;
//sign extension
always_comb
begin
unique case({signExtend_i, immediate_data[15]})
2'b0? : imm_data_extended = {{16{1'b0}}, immediate_data};
2'b10 : imm_data_extended = {{16{1'b0}}, immediate_data};
2'b11 : imm_data_extended = {{16{immediate_data[15]}}, immediate_data};
endcase
end
//Input going to Register file
always_comb
begin
case(regDest)
1'b0: wr_reg_addr = rt;
1'b1: wr_reg_addr = rd;
endcase
end
//Control logic
always_comb
begin
casez({opcode, func})
{6'h00, 6'h20} : ADD = 1;
{6'h08, 6'b??????} : ADDI = 1;
{6'h00, 6'h24} : AND = 1;
{6'h0C, 6'b??????} : ANDI = 1;
{6'h04, 6'b??????} : BEQ = 1;
{6'h07, 6'b??????} : BGTZ = 1;
{6'h05, 6'b??????} : BNE = 1;
{6'h02, 6'b??????} : J = 1;
{6'h00, 6'h8} : JR = 1;
{6'h23, 6'b??????} : LW = 1;
{6'h00, 6'h27} : NOR = 1;
{6'h00, 6'h25} : OR = 1;
{6'h00, 6'h2A} : SLT = 1;
{6'h0A, 6'b??????} : SLTI = 1;
{6'h00, 6'h03} : SRA = 1;
{6'h00, 6'h22} : SUB = 1;
{6'h2B, 6'b??????} : SW = 1;
{6'h00, 6'h26} : XOR = 1;
{6'h0E, 6'b??????} : XORI = 1;
endcase
end
endmodule
jump is x because J is x. A logic signal initializes to x at time 0. My guess is that your casez never activates the J = 1 line, so J remains x.
module tb;
logic J;
assign jump = J ? 1'b1:1'b0;
initial begin
#5;
$display($time, " J=%b jump=%b", J, jump);
end
endmodule
Output:
5 J=x jump=x