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verilogxilinx-isecarryflag

16-bit adder from 4-bit Carry Look Ahead (CLA) - Cout from Block Generate and Propagate

I'm new to Verilog. Here's what I have done so far and the 4-bit CLA works. However, the 16-bit (using instances of 4-bit CLA) doesn't. The problem is definitely in setting the Cout_itermed (intermediate carries) values from block propagate (BP) and block generate (BG). I've created a module carries to deal with this.

In Xilinx ISE, the output waveform shows up as this (no wave shown):

Xilinx ISE

module CLA_4bit(
        output [3:0] S,
        output Cout, PG, GG,
        input [3:0] A, B,
        input Cin
        );

        wire [3:0] G,P,C;

        assign G = A & B; //Generate
        assign P = A ^ B; //Propagate

        assign C[0] = Cin;
        assign C[1] = G[0] | (P[0] & C[0]);
        assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);
        assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);

        assign Cout = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |(P[3] & P[2] & P[1] & P[0] & C[0]);
        assign S = P ^ C;

        assign PG = P[3] & P[2] & P[1] & P[0]; // block generate
        assign GG = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]); // block propagate
endmodule

module CLA_16bit(
        output reg [15:0] S,
        output reg Cout,
        input [15:0] A, B,
        input Cin
        );

        reg [3:0] BP, BG;

        reg [3:0] Cout_itermed;

        carries my_carries(BP, GP, Cin, Cout_itermed, Cout);

        CLA_4bit cla0(S[3:0], Cout_itermed[0], BP[0], BG[0], A[3:0], B[3:0], Cin);

        CLA_4bit cla1(S[7:4], Cout_itermed[1], BP[1], BG[1], A[7:4], B[7:4], Cout_itermed[0]);

        CLA_4bit cla2(S[11:8], Cout_itermed[2], BP[2], BG[2], A[11:8], B[11:8], Cout_itermed[1]);

        CLA_4bit cla3(S[15:12], Cout_itermed[3], BP[3], BG[3], A[15:12], B[15:12], Cout_itermed[2]);

        Cout = Cout_itermed[3];
endmodule

module carries (
        input [3:0] BP,
        input [3:0] BG,
        input Cin,
        output reg [3:0] Cout_itermed,
        output reg Cout
        );

        assign Cout_itermed[0] = BG[0] |  (BP[0] & Cin);
        assign Cout_itermed[1] = BG[1] |  (BP[1] & Cout_itermed[0]);
        assign Cout_itermed[2] = BG[2] |  (BP[2] & Cout_itermed[1]);

        assign Cout = Cout_itermed[3]; 

endmodule

The waveform does show up (and correctly) when I run a test bench of the 4 bit CLA. Could anyone explain where the problem lies in the carries or the CLA_16bit module?

Solution

  • Cout_itermed has two drivers - the first being the Cout outputs of a CLA_4bit, and the second being the Cout_itermed output of the carries module.

    The same applies to Cout in CLA_16bit (though it's two drivers end up being the same signal, Cout_itermed[3], in CLA_16bit and carries).

    Remember that in Verilog you're describing physical circuitry, and you should never have two sources (drivers) connected to the same wire - that's how we get short circuits!

    The following is based on https://en.wikipedia.org/wiki/Lookahead_carry_unit#16-bit_adder. What you'll want to do is define remove the Cout_itermed[x] from the Cout port in the CLA_16bits (you can just leave the port hanging). You should move the logic to determine Cout_itermed[3] (i.e. BG[3] | (BP[3]&Cout_itermed[2])) to the carries module.