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genericscompilationvhdlmodelsim

How to define generic value at compile time using Modelsim?


Is it possible to define a generic value at COMPILE time using Modelsim?

I need to compile a file that contains generate statements, which are turned off & on based on the value of my generic boolean.

I have unsuccessfully tried the following compile statement, where is_primary is the boolean variable name:

vcom -work work -is_primary=true file_name.vhd

I have found similar syntax for simulation (vsim), but I do not see a way to define a generic for vcom. Any suggestions?


Solution

  • A generic is just a constant that is passed into an entity through a generic list. You don't compile one toplevel and then compile the other toplevel, you compile a single toplevel and then the test bench with BOTH instantiations. You wire one up to true and the other up to false. Done.

    U0 : entity toplevel generic map (is_primary => true) port map( insert ports here );

    U1 : entity toplevel generic map (is_primary => false) port map( insert ports here );

    Down in your hierarchy, however you cannot CHECK your generics until after elaboration. Run your sim 1 ps then go examine them.