I am trying to make a simple VHDL project to brush up my memory. I am using a file half_adder.vhd to create another file full_adder.vhd, which I wish to simulate. These files are not in the same project. I am using the Xilinx ISE version 14.7.
My code synthesizes perfectly fine, and passes the syntax check. I can also create RTL schematics. However, whenever I try to create a test bench for the full adder, I get the following error messages:
ERROR:HDLParsers:3317 - "E:/workspaceXilinx/FullAdder/full_adder.vhd" Line 23. Library half_adder cannot be found.
ERROR:HDLParsers:3513 - "E:/workspaceXilinx/FullAdder/full_adder.vhd" Line 24. Declaration all can not be made visible in this scope since design unit half_adder is not a package.
I have added half_adder.vhd to the work library, so I'm not sure why the library cannot be found. Here are the two files I am using:
half_adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity half_adder is
port(a, b: in STD_LOGIC;
s, c: out STD_LOGIC);
end half_adder;
architecture Behavioral of half_adder is
begin
s <= a xor b;
c <= a and b;
end Behavioral;
full_adder.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library half_adder;
use half_adder.all;
entity full_adder is
port (a, b, cin: in STD_LOGIC;
s, cout: out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
signal s1, c1, c2: STD_LOGIC:='0';
begin
HA1: entity work.half_adder port map(a, b, s1, c1);
HA2: entity work.half_adder port map(s1, cin, s, c2);
cout <= c1 or c2;
end Behavioral;
The work library refers to the library currently being compiled. If you have not explicitly created a half_adder library in the design tool, it will not exist. All you need to do is remove this library and use clause relating to half_adder; it is not required.