How to code a asynchronous reset in chisel

Question

How to add the reset signal to the sensitivity list in the generated Verilog code when writing a Chisel code, for example the code below for D flip flop:

val x = Reg(init = UInt(0, width = 1))
    x := io.D
    io.Q := x 

will generate a Verilog code as this:

always @(posedge clk) begin
    if(reset) begin
      x <= 1'h0;
    end else begin
      x <= io_D;
    end
end

as seen the reset is synchronous with the clock, how to code Chisel to generate something like this:

always @(posedge clk or posedge reset) begin
    if(reset) begin
      x <= 1'h0;
    end else begin
      x <= io_D;
    end
end

where the reset signal is in the sensitivity list and hence asynchronous.

Edit: As pointed by chrisvp there is another question here and a discussion in chisel-users google group here

Answer 1

This question is a copy of How to generate an asynchronous reset verilog always blocks with chisel

If really required, you could consider forcing this by considering the rst as a second clock domain as described in the Chisel manual , though I wouldn't recommend to do so.