I was going through the MMU code for an ARM processor(ARMv7). They have made use of fully associative and set associative TLB. I am aware of the implementation of Cache using this method. I also read that TLB is nothing but CPU cache. But I am failing to join the pieces as the purpose of TLB and Cache are different. I would like to know how the set and Full associativity works in context of the TLB.
This is globally the same behaviour: TLB use the virtual address and the size as a tag, but instead of storing data, store the attributes of the associative page (Physical address, protection, etc).
Set associative just means that a limited number of pages can share the same tag/attributes, while full associative means that a tag/attribute can be stored at any location in the TLB cache. This is far more efficient, but this can only be done for very small caches.