System-Verilog testbench generate 2 clocks same frequency 90 degrees out of phase

Question

For a system verilog testbench I need to create 2 clocks with the parameters

Clock1 = 250MHz, starting phase 0degrees

Clock2 = 250MHz, starting phase 90degrees w.r.t. Clock1

I tried the following but it had no effect on the clock generation and both are still in phase. How do I achieve this phase shift?

  parameter CLK_PERIOD = 4000; //250MHz = 4000ps

  initial
    Clock1 = 1'b0;
  always
    Clock1= #(CLK_PERIOD/2.0) ~Clock1;

  initial begin
    Clock2 = 1'b0;
    #1000; //to make it 90degrees out of phase with Clock1
  end
  always
    Clock2= #(CLK_PERIOD/2.0) ~Clock2;

Answer 1

Use forever inside the Clock2 initial block:

module tb;
  parameter CLK_PERIOD = 4000; //250MHz = 4000ps
  bit Clock1, Clock2;
  initial
    Clock1 = 1'b0;
  always
    Clock1= #(CLK_PERIOD/2.0) ~Clock1;

  initial begin
    Clock2 = 1'b0;
    #1000; //to make it 90degrees out of phase with Clock1
    forever Clock2= #(CLK_PERIOD/2.0) ~Clock2;
  end
endmodule