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vhdlsimulationfpgamodelsimnetlist

in vhdl case statements,how to deal with 4 value logic?

I am a newer to vhdl, and I'm working for a project.

but something block me recently:

   if reset='0' then 
      prstate<="00";
      else if rising_edge(clock)  then
      case  prstate  is
          when "00"=> 
               if wd_link='1'   then
               prstate<="01";
          when "01"=> 
               (do something and) prstate<="10";
          when "10"=> 
                (do something and) prstate<="11";  
          when "11"=> 
                (do something and) prstate<="00";  
          when others=>   prstate<="00"; ----please pay attention to this line

RTL simulation:

at first,I deleted the last line,but modelsim tell me there are only 4 case statements out of 81.My god,I studied that 1 bit contains 9 values.maybe the last line is used to correct errors? maybe when prstate is "0x" or "xx",this line bring it to 00?ok,maybe.

after synthesizing by synopsys DC,there is a warning(about the case):the default branch of case cannot be reached. hah!i don't know why and i don't care.

Post simulation(using the same testbench and the netlist):

after I set and release the reset input,modelsim showed that another module give the wd_link an "x",which cause a big error=>the prstate<="xx" and xx,and xx,and end to xx...even wd_link recover to 0 or 1.

I guess:DC disagree 4 value logic(01xz) or 9 value logic.so the last line is killed.but what can i do?

Please help me,all you are my god.Thank you! sincerely.

Solution

  • If the value of prstate is always to be well defined ("00", "01", "10" or "11"), then you can propagate any undefined values if you use:

    when others => prstate <= (others => "XX");

    Simulation will then show 'X's in more places in case of a bug, thus making catching easier.

    Synthesis will usually use the 'X's as a freedom to make the netlist smaller or faster, depending on requirements.