"Iteration limit reached at time" when i try to simulate my code

Question

I'm trying to implement Booth Algorithm in VHDL, already run a "paper test" and the code apparently works but when I simulate it I'm not getting the desire results... Then I replace the code to do an A-Shift to test but when I simulate my code I'm getting this error:

Error (suppressible): (vsim-3601) Iteration limit 5000 reached at time 180 ns.

I just replace this line: P := STD_LOGIC_VECTOR(unsigned(P) SRA 1);

For this: P := P(16) & P(16 downto 1);

This is the code atm:

LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY algor_booth IS
    PORT(oper1 :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         oper2 :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         sel :    IN STD_LOGIC;
         result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
            );
END ENTITY;

ARCHITECTURE algor OF algor_booth IS
BEGIN
    PROCESS (sel)
        VARIABLE A, S, P: STD_LOGIC_VECTOR(16 DOWNTO 0);
        VARIABLE Ma2: STD_LOGIC_VECTOR(7 DOWNTO 0);
        --VARIABLE flag: STD_LOGIC;
    BEGIN

        IF sel = '0' THEN
            Ma2 := (NOT oper1) + 1;
            A   := oper1 & "00000000" & '0';
            S   := Ma2 & "00000000" & '0';
            P   := "00000000" & oper2 & '0';
        ELSE
            --flag := '0';
            FOR i IN 1 TO 8 LOOP
                IF P(1 DOWNTO 0) = "01" THEN
                    P := P + A;
                    --flag := '0';
                    --P(17) := flag;
                ELSIF P(1 DOWNTO 0) = "10" THEN
                    P := P + S;
                    --flag := '1';
                    --P(17) := flag;
                END IF;
                --P(17) := flag;
                P :=    P(16) & P(16 downto 1);
                --P(17) := flag;
            END LOOP;
            result <= P(16 DOWNTO 1);

        END IF;
    END PROCESS;
END algor;

Answer 1

After trying a lot, just changed this line: P := P(16) & P(16 downto 1);

For this one: P(16 downto 0) := P(17 downto 1);

And problem solved!

Here is the fixed code:

LIBRARY IEEE;
    USE IEEE.STD_LOGIC_1164.ALL;
    USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY algor_booth IS
    PORT(oper1 :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         oper2 :  IN STD_LOGIC_VECTOR(7 DOWNTO 0);
         sel :    IN STD_LOGIC;
         result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
            );
END ENTITY;

ARCHITECTURE algor OF algor_booth IS
BEGIN
    PROCESS (oper1, oper2)
        VARIABLE A, S, P: STD_LOGIC_VECTOR(17 DOWNTO 0);
        VARIABLE Ma2: STD_LOGIC_VECTOR(7 DOWNTO 0);
        VARIABLE flag: STD_LOGIC;
    BEGIN
            Ma2 := (NOT oper1) + 1;
            A   := '0' & oper1 & "00000000" & '0';
            S   := '0' & Ma2 & "00000000" & '0';
            P   := '0' & "00000000" & oper2 & '0';  
            flag := '0';

            FOR i IN 1 TO 8 LOOP
                IF (P(1) = '0' AND P(0) = '1') THEN
                    flag := '0';
                    P(17) := flag;
                          P := P + A;
                ELSIF (P(1) = '1' AND P(0) = '0') THEN
                    flag := '1';
                    P(17) := flag;
                          P := P + S;
                END IF;
                P(17) := flag;
                P(16 downto 0) := P(17 downto 1);
                P(17) := flag;
            END LOOP;
            result <= P(16 DOWNTO 1);
    END PROCESS;
END algor;

Thanks for your help guys!