Level-sensitive SR Latch behavior
I am looking into the difference between a regular SR latch and a level sensitive SR Latch.
I am aware that what we want to avoid in an SR latch is the configuration (1,1) because it can cause an oscillation and when it finally settles on a 0 or 1 we can't be certain which one due to the oscillation. Thus, we use a level sensitive SR latch. But can someone elaborate on the behavior of this level-sensitive SR latch. Because if S,R, and C(usually a clock) are all 1, it seems to me that we can still end up with the same (1,1) configuration that we are trying to avoid.
I have found this post and it talks about the difference between a latch and a flip-flop. But just to re-iterate, my main question is if clk = 1 and if S =1, R =1, then can't we still end up in a loop of oscillations.
The SR flipflop is designed so that C is only 1 when S and R are stable. It is designed very carefully as to prevent C from being 1 when S=R=1. However, this is not apparent at all given the basic diagram of the flip flop.
An improvement to this is the D flipflop. It inverts one of the signals from the SR flipflop. This ensures that S and R are never the same. This can be seen in the image below.
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