Illegal syntax for subtype indication VHDL200X

Question

I am trying to create a "dynamic" 2D array which I can set with generics in my entity.

I followed the example in https://s3.amazonaws.com/verificationhorizons.verificationacademy.com/volume-8_issue-3/articles/stream/vhdl-2008-why-it-matters_vh-v8-i3.pdf on page 32.

The declaration of my type within the package (TypeDeclarations):

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package TypeDeclarations is

-- Type BusArray -----------------------------------------------------
-- Can be used by: DArray((Y - 1) downto 0)((X - 1) downto 0);      --
                                                                    --
    type TArray is array (natural range <>) of std_logic_vector;    --
                                                                    --
----------------------------------------------------------------------
end package;

my entity:

-- Libraries
library ieee;
use ieee.std_logic_1164.all;

-- Own libraries
use work.TypeDeclarations.all;

entity DynamicRegisterSet is
    generic (
        INPUT_DATAWIDTH  : integer := 1;
        OUTPUT_DATAWIDTH : integer := 8;
        N_REGISTERS      : integer := 1);
    port (
        MCLK : in std_logic := '0';
        WE   : in std_logic := '0';

        -- input data
        DATA : in std_logic_vector((INPUT_DATAWIDTH-1) downto 0) := (others => '0');
        SEL  : in integer range 0 to (INPUT_DATAWIDTH-1) := 0;

        -- in/output data (register set)
        REGISTERSET : inout TArray((N_REGISTERS-1) downto 0)((OUTPUT_DATAWIDTH-1) downto 0) := (others => (others => '0')));
end DynamicRegisterSet;

This is the first time I'm using the updated compiler (VHDL200X), I don't think I am doing this wrong but else I wouldn't get this message:

VHDL\CommonBlocks\DynamicRegisterSet\Sources\DynamicRegisterSet.vhd" Line 25: Illegal syntax for subtype indication

Anyone any suggestions? I would appreciate it very much, thanks!

Answer 1

Xilinx ISE 14.7 has no VHDL-2008 support...

They support a hand full of VHDL-2002/2008 features, but unconstrained array elements are not supported.

Vivado added VHDL-2008 support in 2016.1 and sets it as default. But as far as I can see, it's no full VHDL-2008 support.

There is a Xilinx XST synthesis user guide listing these features in the VHDL section. (Sorry I don't have the UG number on my phone.)