Generate random enum using system Verilog

Question

typedef enum int { IPV4_VERSION = 0, IPV4_IHL = 1, IPV4_TOTAL_LENGTH = 2,IPV4_CHECKSUM = 3 } ipv4_corrupton;

ipv4_corrupton ipv4_corrupt;

std::randomize(ipv4_corrupt) with {ipv4_corrupt dist { IPV4_VERSION :=2,IPV4_IHL := 4,IPV4_TOTAL_LENGTH := 4,IPV4_CHECKSUM := 2}; };

I ran the above code 10 times and always got IPV4_CHECKSUM. I am making any mistake?

Answer 1

I modified your code a bit and got the expected output.

module test;

  typedef enum int { IPV4_VERSION = 0, IPV4_IHL = 1, IPV4_TOTAL_LENGTH = 2,IPV4_CHECKSUM = 3 } ipv4_corrupton;

  ipv4_corrupton ipv4_corrupt;

  initial begin

    repeat(10) begin

      #1

      std::randomize(ipv4_corrupt) with {ipv4_corrupt dist { 0 :=2,1 := 4,2:= 4,3:= 2}; };

      $display ("Value is %s",ipv4_corrupt);

    end

   end

endmodule

Output:

Value is IPV4_VERSION

Value is IPV4_IHL

Value is IPV4_TOTAL_LENGTH

Value is IPV4_IHL

Value is IPV4_VERSION

Value is IPV4_TOTAL_LENGTH

Value is IPV4_CHECKSUM

Value is IPV4_TOTAL_LENGTH

Value is IPV4_IHL

Value is IPV4_IHL