VHDL Finite State Machine

Question

How can I implement a VHDL code that designs a finite state machine without letting the compiler knows it's a finite state machine. In the code given you'll see how we implemented the FSM in class, but it showed the state diagram in the RTL viewer, how can I not let the compiler know it's a FSM and not draw the state diagram. Moreover, my professor said that the design will be faster if the compiler doesn't recognise the FSM.

library IEEE;  
use IEEE.std_logic_1164.all; 

entity fsm is  
  port ( clk, reset, x1 : IN std_logic;  
                    outp : OUT std_logic);  
end entity;  
architecture beh1 of fsm is  
  type state_type is (s1,s2,s3,s4);  
  signal state, next_state: state_type ;  
begin 
  process1: process (clk,reset)  
  begin  
    if (reset ='1') then  
      state <=s1;  
    elsif (clk='1' and clk'Event) then  
      state <= next_state;  
    end if;  
  end process process1; 

  process2 : process (state, x1)  
  begin  
    case state is  
          when s1 => if x1='1' then   
                        next_state <= s2;  
                      else  
                        next_state <= s3;  
                      end if;  
          when s2 => next_state <= s4;  
          when s3 => next_state <= s4;  
          when s4 => next_state <= s1;  
    end case;  
end process process2; 

process3 : process (state)  
  begin  
      case state is  
          when s1 => outp <= '1';  
          when s2 => outp <= '1';  
          when s3 => outp <= '0';  
          when s4 => outp <= '0';  
      end case;  
end process process3;  
end beh1; 

Answer 1

The synthesized design is not neccessarily faster or smaller if the state machine extraction is disabled because the synthesis compiler can choose from several encodings when synthesizing a state machine. You can turn off the state machine extraction via menu "Assignments" -> "Settings" -> "Analysis & Synthesis Settings" -> "More Settings" -> "Extract VHDL State Machines".

Let's start with the default setting where the extraction is on. If we use a Cyclone IV FPGA for example, the synthesis compiler will choose a one-hot encoding for the state-machine. You will see it in the Compilation Report under "Analysis & Synthesis" -> "State Machines". 4 combinational functions (LUTs) and 3 logic registers are required. A first estimate of the speed of the design can be deduced from the synthesized netlist accessible via menu "Tools" -> "Netlist Viewers" -> "Technology Map Viewer (Post-Mapping)":

(clickable)

As we see, there is a maximum of:

• 1 levels of logic between any two registers
• 1 levels of logic between an input and an register
• 1 levels of logic between an output and an register

So it is pretty fast and the final timing will merely depend on the routing delay.

If we disable the FSM extraction, then only 2 LUTs and 2 registers are required because state is now encoded binary. The netlist will look like:

(clickable)

There was a small improvement: the output can now be directly driven by register state[1]. So your design will now likely have a smaller clock-to-output time.

Here an improvement was possible after the state machine extraction was turned off. But, this is not generally the case because it all depends on the actual encoding of the type state_type. If we leave the FSM extraction disabled and change the declaration of state_type to:

  type state_type is (s3,s1,s2,s4);  

Then the synthesis result is worse again: 3 LUTs and 2 registers are required, and 1 level of logic between an register and the output.