How to run simulation for a set amount of clock cycles

Question

To all, I am new to VHDL. I have a working design however my simulation keeps running forever until I cancel the simulation. In the test bench how do I stop the simulation after x clock cycles? Is this done in the clock process?

clk_process :process
  begin
     clk <= '0';
     wait for clk_period/2;  
     clk <= '1';
     wait for clk_period/2;  
end process;

Please and Thank you!

Answer 1

In VHDL-2008 :

if now >= clk_period * x then 
   std.env.stop;
end if;

In earlier revisions (still works in 2008 though!) :

assert now < clk_period * x report 
    "Stopping simulation : this is not a failure!" severity failure;

This latter curiosity (abusing an assert) is actually recommended in Janick Bergeron's book "Writing Testbenches"!

The clock process is as good a place as any for them but a separate process (probably sensitive to clock) for simulation control may be marginally cleaner design.