vhdlxilinxmodelsim
Unexplained Red X's (collisions?) with Dual-Port BRAM in Xilinx ISim
I've read up on this quite a bit and I can't figure out why I would have Red X's (Collisions?) with a simple Dual-Port BRAM IP core.
I think there are only a few scenarios that can cause this:
Multiple sources: I checked and I don't have multiple sources diving current_row_data_out. I only read from it.
Simultaneous Read + WRite to the same address: Nope. As you can see in the image, read_addr and write_addr are always different.
What else can it be?
Solution
The issues was caused by one or two writes of uninitialized data all the way in the beginning of the simulation. It created a chain-reaction that didn't show up until later because the values read in the beginning were coincidentally correct.
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