I am developing a Linux kernel module that interfaces with a hardware component accessing the DDR using DMA. (running on an arm SoC)
What the driver essentially does is allocate a buffer (w/ kmalloc), and write the physical (using virt_to_phys) address of the buffer to the underlying hardware
When reading the buffer, the old data seems to get read, which points to a cache problem (when inspecting the DDR directly, bypassing Linux, the new data is read).
I can't seem to understand how cache flushing / invalidation works.
What is the best approach?
Using kernel 3.14
You have 2 options:
use coherent mapping that is allocate memory using dma_alloc_coherent
use streaming mapping that is map the buffer for dma using dma_map_single telling the kernel the DMA direction and unmap it after you finish