I got top module including sub-modules instantiated in testbench file. The sub-modules are pretty free on their own, therefore when I am testing the top module, I need to introduce only few signals and track few outputs, but the top module has many other ports.
May I provide some "default"/"undefined" signal (and sink) to those pins (not regarding their size, type)?
There are 2 ways I solve that right now, either take out the sub-module to test it (well, but I want to test it within top module) or write appropriate "zero" inputs for inputs and introduce signals for outputs (lot of work as well).
using VHDL with Vivado 2015
alright, so this is the testbench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity tb_FIR_v0_3 is
end tb_FIR_v0_3;
architecture Behavioral of tb_FIR_v0_3 is
shared variable C_S00_AXI_DATA_WIDTH : integer := 32;
shared variable C_S00_AXI_ADDR_WIDTH : integer := 7;
component FIR_v0_3 is
generic (
C_S00_AXI_DATA_WIDTH : integer := 32;
C_S00_AXI_ADDR_WIDTH : integer := 7
);
port (
fir_clk : in std_logic;
fir_x_in : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
fir_y_out : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
fir_d_out : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
-- User ports ends
s00_axi_aclk : in std_logic;
s00_axi_aresetn : in std_logic;
s00_axi_awaddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_awprot : in std_logic_vector(2 downto 0);
s00_axi_awvalid : in std_logic;
s00_axi_awready : out std_logic;
s00_axi_wdata : in std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_wstrb : in std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
s00_axi_wvalid : in std_logic;
s00_axi_wready : out std_logic;
s00_axi_bresp : out std_logic_vector(1 downto 0);
s00_axi_bvalid : out std_logic;
s00_axi_bready : in std_logic;
s00_axi_araddr : in std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
s00_axi_arprot : in std_logic_vector(2 downto 0);
s00_axi_arvalid : in std_logic;
s00_axi_arready : out std_logic;
s00_axi_rdata : out std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
s00_axi_rresp : out std_logic_vector(1 downto 0);
s00_axi_rvalid : out std_logic;
s00_axi_rready : in std_logic
);
end component FIR_v0_3;
signal e_clk : std_logic := '1' ;
signal e_reset : std_logic := '1' ;
signal e_x_in : std_logic_vector (31 downto 0);
signal e_y_out : std_logic_vector (31 downto 0);
signal e_d_out : std_logic_vector (31 downto 0);
signal s00_axi_awready : std_logic;
signal s00_axi_wready : std_logic;
signal s00_axi_bresp : std_logic_vector(1 downto 0);
signal s00_axi_bvalid : std_logic;
signal s00_axi_arready : std_logic;
signal s00_axi_rdata : std_logic_vector(32-1 downto 0);
signal s00_axi_rresp : std_logic_vector(1 downto 0);
signal s00_axi_rvalid : std_logic;
signal s00_axi_aclk : std_logic := '0';
signal s00_axi_aresetn : std_logic;
signal s00_axi_awaddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_awprot : std_logic_vector(2 downto 0);
signal s00_axi_awvalid : std_logic := '0';
signal s00_axi_wdata : std_logic_vector(C_S00_AXI_DATA_WIDTH-1 downto 0);
signal s00_axi_wstrb : std_logic_vector((C_S00_AXI_DATA_WIDTH/8)-1 downto 0);
signal s00_axi_wvalid : std_logic := '0';
signal s00_axi_bready : std_logic := '0';
signal s00_axi_araddr : std_logic_vector(C_S00_AXI_ADDR_WIDTH-1 downto 0);
signal s00_axi_arprot : std_logic_vector(2 downto 0);
signal s00_axi_arvalid : std_logic := '0';
signal s00_axi_rready : std_logic := '0';
begin
inst_FIR_v0_3 : FIR_v0_3
generic map (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 7
)
port map (
-- Users to add ports here
fir_clk => e_clk,
fir_x_in => e_x_in,
fir_y_out => e_y_out,
fir_d_out => e_d_out,
-- Ports of Axi Slave Bus Interface S00_AXI
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => e_reset,
s00_axi_awaddr => ( others => '0' ),
s00_axi_awprot => ( others => '0' ),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => ( others => '0' ),
s00_axi_wstrb => ( others => '0' ),
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => ( others => '0' ),
s00_axi_arprot => ( others => '0' ),
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
process
variable count : integer := 0;
begin
if ( count = 0 ) then
-- e_reset <= '0'; -- VALUES NOT INITIATED PROPERLY, FUCKER ? ... With the non-stop, pop pop and stainless steel (DMX)
e_x_in <= x"00000000";
end if;
if ( count = 3 ) then
-- e_reset <= '1';
end if;
if ( count = 3 ) then
e_x_in <= x"00000001";
end if;
if ( count = 5 ) then
e_x_in <= x"00000000";
end if;
if ( count = 8 ) then
e_x_in <= x"00000000";
end if;
e_clk <= not(e_clk);
wait for 0.5 ns;
count := count + 1;
if( (count = 60) ) then
count := 0;
end if;
end process;
end Behavioral;
I am too lazy to create signal for every AXI input/output ports and then connect them one by one. May I avoid somehow creating those 21 signals ...
signal s00_axi_awready : std_logic;
signal s00_axi_wready : std_logic;
signal s00_axi_bresp : std_logic_vector(1 downto 0);
signal s00_axi_bvalid : std_logic;
signal s00_axi_arready : std_logic;
....
...
and then connecting them ? Like this ...
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
Is there any "universal" in/out signal that I would tie to pins that are not important, because I cant leave the ports of an instance unconnected (as far as I know and tried).
If I understand the question correctly, inputs in your port definition can have default values, and outputs can be left unconnected in an instantiation. For example:
entity ShiftRegister is
Generic (
WIDTH : integer
);
Port (
clk : in STD_LOGIC;
enable : in STD_LOGIC := '1';
serial_in : in STD_LOGIC := '0';
parallel_out : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
);
end ShiftRegister;
...
SR : entity work.ShiftRegister
Generic map (
WIDTH : integer => 8
)
Port map(
clk => serial_clk,
serial_in => serial_data_in
);
In this example, the register will always be enabled, and the entity does not output anything. Not a very useful instantiation in this case, but I think this answers your question!