calculating delay cycles for hcs12

I try to calculate number of instruction cycles and delay cycles for HCS12. I have some information about HCS12

The HCS12 uses the bus clock (E clock) as a timing reference.

The frequency of the E clock is half of that of the onboard clock oscillator (clock, 48 MHz, E-clock, 24 MHz).
Execution times of the instructions are also measured in E clock cycles

I wonder the 24Mhz is crystal frequency? If so, only half of the crystal’s oscillator frequency is used for CPU instruction time. So, should it be halved?
How can I make 100-ms time delay for a demo board with a 24-MHz bus clock?

In order to create a 100-ms time delay, we need to repeat the preceding instruction sequence 60,000 times [100 ms ÷ (40 ÷ 24,000,000) μs = 60,000]. The following instruction sequence will create the desired delay: There is an example but I don't understand how 60000 and 40 values are calculated.

           ldx #60000       
loop       psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           psha              ; 2 E cycles
           pula              ; 3 E cycles
           nop               ; 2 E cycles
           nop               ; 3 E cycles
           dbne x,loop

Solution

Your first section explains that if the internal oscillator (or external crystal) is 48 MHz, the EClock is 24 MHz. So if you want to delay by 100 millisec, that is 24,000,000 * 100 / 1,000 EClocks, namely 2,400,000 instruction cycles.

The maximum register size available is 16-bits, so a loop counter value is chosen that is <= 65535.

Conveniently 60,000 is a factor of 2,400,000 being 60,000 * 40. So the inner loop is contrived to take 40 cycles. However the timing comments on the last 3 lines are incorrect, they should be

nop               ; 1 E cycle
nop               ; 1 E cycle
dbne x,loop       ; 3 E cycles

Giving the required 40 cycles execution time.

Note that if you have interrupts, other processes, this hard coded method is not very accurate, and a timer interrupt would be better.