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Errors about using buffer in VHDL project

I am a beginner to VHDL. I am trying to implement a simple project but I got some errors. The first one is about using buffers.

This is my entity code:

entity Demultiplexer is
Port ( A : in  STD_LOGIC;
       S : in  STD_LOGIC_VECTOR (2 downto 0);
       I0 : out  STD_LOGIC;
       I1 : out  STD_LOGIC;
       I2 : out  STD_LOGIC;
       I3 : out  STD_LOGIC;
       I4 : out  STD_LOGIC;
       I5 : out  STD_LOGIC;
       I6 : out  STD_LOGIC;
       I7 : out  STD_LOGIC);
end Demultiplexer;

and this is my architecture:

architecture Behavioral of Demultiplexer is
begin
    I0 <= A WHEN S = "000" ELSE
    I1 <= A WHEN S = "001" ELSE
    I2 <= A WHEN S = "010" ELSE
    I3 <= A WHEN S = "011" ELSE
    I4 <= A WHEN S = "100" ELSE
    I5 <= A WHEN S = "101" ELSE
    I6 <= A WHEN S = "110" ELSE
    I7 <= A WHEN S = "111";
end Behavioral;

This the error list

ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments- 1\Demultiplexer.vhd" Line 49: Cannot read from 'out' object i1 ; use   'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 49: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 50: Cannot read from 'out' object i2 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 50: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 51: Cannot read from 'out' object i3 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 51: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 52: Cannot read from 'out' object i4 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 52: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 53: Cannot read from 'out' object i5 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 53: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 54: Cannot read from 'out' object i6 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 54: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:288 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 55: Cannot read from 'out' object i7 ; use 'buffer' or 'inout'
ERROR:HDLCompiler:1731 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 55: found '0' definitions of operator "<=", cannot determine exact overloaded matching definition for "<="
ERROR:HDLCompiler:854 - "H:\SetUpSoftwares\XilinxProjects\Assignments-1\Demultiplexer.vhd" Line 45: Unit <behavioral> ignored due to previous   errors.
Solution

  • You have your conditional assignments wrong. The syntax is

    i0 <= a when s = "000" else other_value;  -- whatever your code is supposed to do
i1 <= a when s = "001" else other_value;
...

    The (a little misleading) error message is caused by the i1 assignment in the next line:

    i0 <= a when s = "000" else i1 ...

    This is as the code was understood (until it completely bailed out) and this would mean you are trying to read from an out signal which is not supported until VHDL 2008.