nested for loops in verilog that second for loop depends upon output of first for loop

Question

I'm developing a verilog code for cumulative histogram method , for median filter . it uses nested for loops , that the input of second for loop depends on output of first for loop . the problem lies here .the second for loop is not accepting that input . please help. the code is

module median(a, b,k,n,h);
    input  [4:0] a;
    output [255:0] b;
    output k,n,h;
    reg [255:0] b;
    reg [255:0]k,n,h;

    always @(a) begin
      for (n=0;n < 256;n=n+1)
        b[n]=0;
      for (n=0;n<=4;n=n+1) begin
        b[a[n]]=b[a[n]]+1;
        h=a[n]+1;
        for ( k = h;k <=255;k = k+1) begin
          b[k]=b[k]+1;
        end
      end
      for (n=0;n<=255 ;n=n+1) begin
        if(b[n]==3)begin
          $display ("the median is %d",n);
        end
      end
    end
 endmodule

Answer 1

Just looking at this section of code:

for (n=0;n<=4;n=n+1) begin
    b[a[n]]=b[a[n]]+1;

n is 256 bits, but for this loop only goes from 0 to 4.
This selects a value from a (5 bits), so we are selecting bit 0 to 4 of a.

Each selection of a is 1 bit containing either a 0 or 1, therefore we are selecting and incrementing either b[0] or b[1] on each iteration of the for loop.

However b is also 256 bits so b[0] and b[1] are also 1 bit values, when incrementing they are going to toggle between 1 and 0.

I am guessing the above behaviour is not intended and that you actually want to be using vectors:

reg [255:0] b [0:4) ;

Above b has 5 selectable positions each holding a 256 bit integer. This means that b[0] will be a 256 bit integer and not a 1 bit integer as your current example.