How does having unique Data & Instructions memory affects us to the standard 5-stage Pipeline?What about with & without Forwarding?
What's the advantage of having a different memory for each?
Regardless of having Forwarding, if you only have one port to access memory (e.g. unique Data & Instruction memory bus) and to simplify let's say there is no cache in the system (so every memory access needs to use the memory unit) then every instruction that needs the MEM stage to use the memory bus will generate a structural hazard, as the CPU won't be able to perform the FETCH and MEM stages in parallel because they both need to access memory.
If instead you have two ports to access memory (e.g, one for Instructions and another for data), then the structural hazard noted above will be avoided as each memory-access stage will use its own bus+memory.