In SystemVerilog test-benches how do I best describe multi-cycle transactions that can be interleaved

Question

I would like to describe transactions using tasks. I am using a clockingblock cb. This task is kind-of what I want to do, but the value of write seams to be random when doing like this, I guess there is no defined ordering on who gets to drive write last.

task automatic write_trans(input int data);
    fork
        begin
            cb.write <= '1;
            cb.data <= data;
        end
        begin
            ##1;
            //But only if there is no other transactions driving write to 1
            cb.write <= '0; 
        end
    join_any
endtask

So if I run just a single transaction write goes low the next clock cycle.

//for isolated transactions write should be 0,1,0;
write_trans('h17);
##2;
//for these two transactions write should be 0,1,1,0;
write_trans('h18);
##1;
write_trans('h19);

Answer 1

The last drive statement wins, based on the order the the drive statements are executed within the slot they are scheduled to mature (update). You can write your task as follows:

task automatic write_trans(input int data);
  cb.write <= '1;
  cb.data <= data;
  cb.write <= ##1 '0; 
endtask

This is explained in the 1800-2012 LRM §14.16.2 Driving clocking output signals.