VHDL - WAIT ON <signal> statement

I'm trying to work through an example of the WAIT ON statement. Every time I try to compile my code the the compiler, Quartus II gives me the following error message.

Error (10533): VHDL Wait Statement error at T1.vhd(23): Wait Statement must contain condition clause with UNTIL keyword

The model Architecture is below. Its function is not important only the reason why the compiler is asking for a UNTIL statement. All the examples I have seen, internet and books show its use as such below:

ARCHITECTURE dflow OF T1 IS
SIGNAL middle   : std_logic;
BEGIN
P1 : PROCESS IS
BEGIN
        IF CLK = '1' THEN
            middle <= input;
        END IF;
    WAIT ON CLK;
END PROCESS P1;
OUTPUT <= MIDDLE;
END ARCHITECTURE dflow;

Solution

I think the basic problem here is that the line

WAIT ON CLK;

is waiting for any type of event on CLK. This could be a transition from 'H' to '1', for example, or it could be either a rising OR falling edge of CLK. In either of these cases, there is no real hardware in the FPGA that can work in this way. It may seem obvious to you that you are looking for a rising edge, because of the if CLK = '1' line, but this is not how the synthesis tool is seeing it.

By adding an until, you can narrow down which particular event you are interested in, hopefully selecting something that can actually be realised in the FPGA. Examples:

wait on clk until clk = '1'; -- Detect a rising edge, OK (ish, see below)
wait on clk until clk = '0'; -- Detect a falling edge, OK (^^)

This method is analogous to the clk'event and clk = '1' technique of edge detection. This is not a recommended method, because you can get a simulation mismatch with reality due to the simulator responding to transitions from 'H' to '1' (among other possibilities), something the hardware cannot do.

The recommended method of detecting edges is with the rising_edge and falling_edge functions:

wait until falling_edge(clk); -- OK, no ambiguity here.

Finally, the whole structure represented here looks pretty non-standard. The common way to write a clocked process is like this:

process (clk)
begin
  if (rising_edge(clk)) then
    -- Do something
  end if;
end process;