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verilogfpgaintel-fpga

Maximum clock frequency on DE1-SOC

What is the maximum clock frequency that can be generated with Altera PLLs in DE1-SOC board?

Solution

  • I can't find a reference to a maximum PLL frequency in any of the Cyclone V documentation. However, it appears (from my own experimentation) that the Altera PLL megafunction/IP Core won't product a generated clock with a frequency faster than 1.6 GHz (1600 MHz).

    That said, I doubt you'll be able to clock any CV circuitry (even fully pipelined) that quickly.