In the past I've used some Xilinx FPGAs and was able to easily create RELATIVE placement of flip-flips using VHDL attributes such as RLOC.
Currently I'm working with the SmartFusion2 FPGA and trying to achieve the same in Libero SoC. After looking through "Synopsys FPGA Synthesis Synplify Pro for Microsemi Edition: Attribute Reference", I was able to find "alsloc" which seems to be the direct equivalent of RLOC.
However the addition of this attribute doesn't change or affect the placement of the MACROs at all.
Looking further I found that "set_location" constraint can be used within the design constraint file to fix the location of MACROs. Unfortunately this constraints the position of the MACROs to an ABSOLUTE position on the chip and can interfere with the rest of automatic placement and routing optimization effort.
So is there a way to constraint the relative position of MACROs (specifically flip-flops) in Libero SoC using VHDL attributes or design constraint file directives?
To my knowledge, there is no direct equivalent. The closest thing would probably be the define_region/assign_region constraints.
Use "assign_region" to associate a set of related flip-flops or entire component instances to a user defined region. "define_region" specifies the size and location for the region. Libero will place the associated parts inside the region.
The region still has an absolute position, but to move the flip-flops around, you only need to change the "define_region" constraint. It is not as elegant as RLOC, but it does the job.