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memoryarmembeddedcortex-a

Unexpected DRAM behavior when MCU stopped at breakpoint

I am currently working on a Freescale Vybrid (VF6xx) MCU, trying to configure an external LPDDR2 DRAM chip.

I am experiencing some odd behavior from the DRAM (memory mapped to 0x8000_0000): When stopped at a breakpoint, the DRAM still seem to change every time i read from it in the debugger.

ARM DS-5 memory view of DRAM, refreshing at 1s intervals.

Does anyone know what might cause this?

Cheers!

Solution

  • I eventually found an answer to the issue.

    As it turned out, the DRAM setup defined wrong address pin. The manufacturer provided a recommended value for the register defining this bit, but this turned out to be wrong.

    For future googlers: The Vybrid Reference Manual Revisions 7 & 8 recommends DDRMC_CR73[APREBIT]=0xA for both DDR3 and LPDDR2. This assigns DDR_A10/CA10 as the address pin. The JEDEC standard specifies DDR_A0/CA0 as the address pin, thus the correct value should be: DDRMC_CR73[APREBIT]=0x0.