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system-veriloguvm

initialize systemverilog (ovm) parameterized class array

I want to monitor several analysis ports, and "publish" the item through one analysis port. It works for predefined item type, but fail to be parameterized.

The code:

   class ovm_analysis_sink #(int NUM_PORTS = 1, type T = ovm_object ) extends ovm_component;

 // .......................................
 `ovm_component_param_utils(ovm_analysis_sink#(NUM_PORTS,T))
 // .......................................

 ovm_analysis_imp #(T,ovm_analysis_sink) mon_analysis_imp[NUM_PORTS-1:0];
 ovm_analysis_port #(T) mon_analysis_port = new("mon_analysis_port", this);

 virtual function void build() ;
 string inst;
for(int i=0 ;i < NUM_PORTS ;i++ )
  begin 
    $sformat(inst,"mon_analysis_imp_%0d",i);
mon_analysis_imp[i] = new(inst,this);
  end

super.build() ;

endfunction : build

The usage of the analysis_sink:

 ovm_analysis_sink #(3,a_type) a_item_sink;

And the error message:

Error-[ICTTFC] Incompatible complex type usage ovm_tb.sv, 42
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the function. 
The type of the actual is 'class $unit::ovm_analysis_sink#(3,class $unit::a_type)', 
while the type of the formal is 'class $unit::ovm_analysis_sink#(1,class ovm_pkg::ovm_object)'. 
Expression: this  Source info: ovm_analysis_imp::new(inst, this)
Solution

  • The error says type incompatibility. That means the actual (run-time) and formal (compile-time) arguments/types of implementation port is not the same.

    There is an error while declaration of analysis port. Declaring the port as shown above creates a handle of analysis imp port of type uvm_analysis_sink #(1,uvm_object) while, you want it to be of type uvm_analysis_sink #(3,a_type).

    So, declare it as follows:

    ovm_analysis_imp #(T,ovm_analysis_sink#(NUM_PORTS,T)) mon_analysis_imp[NUM_PORTS-1:0];

    This shall remove the type conflict and make it type assignment compatible. Now any parameter overriding shall work.

    I have created a sample UVM code on EDAPlayground for reference. Similar applies to your OVM testbench. For further information refer to this forum question.