My following vhdl module will synthesize if I comment out the second process block, but if I try to use both of them, the synthesis will fail with no critical warnings or errors listed. There are some warnings, but they are just the usual things (no ethernet connected for the Zynq, things that aren't used, etc.)
I can not see any reason why this would happen. Originally I had a for loop inside the process statement that was causing the errors, but taking that out did not work.
Then I thought that it might be a multidriven net between the two processes, but that is not the case either.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.NUMERIC_STD.all;
use ieee.std_logic_unsigned.all;
use work.DataTypes_pkg.all;
entity EvalFUOutputs is
Port (
Clk_Launch : in std_logic;
RESET : in std_logic;
start : in std_logic;
current_phase : in PhaseType;
ready : out std_logic;
init_or_captured : in std_logic; --mode bit
all_timings_done : out std_logic;
Capture_vals : in std_logic_vector(FU_OUTPUT_WIDTH_NB-1 downto 0);
Launch_MUXCtrl : in std_logic;
Capture_ClkEn : in std_logic;
--2D array for results.
row_timings : out RowResultsType;
glitches : out OutRowType
);
end EvalFUOutputs;
architecture beh of EvalFUOutputs is
type mode_enum is (init, eval);
signal mode : mode_enum;
type eval_enum is (idle, eval_begin, get_time, all_timed);
signal eval_state : eval_enum;
type init_enum is(begin_init, compare, done);
signal init_state : init_enum;
signal row_time : RowResultsType;
type init_vals_declare is array (0 downto 1) of std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0);
signal init_vals : init_vals_declare;
signal has_been_timed : std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0 );
--
-- if 0 => will not change
-- if 1 => will change
--
signal will_change : std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0);
signal init_done :std_logic;
signal fu_vals_changed : std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0);
--
-- This modules clock signal
--
signal clk : std_logic;
signal a : std_logic;
begin
clk <= Clk_Launch;
mode_of_FU :
process(clk, mode, RESET) is
begin
if rising_edge(clk) then
if RESET = '1' then
--TODO:RESET LOGIC
mode <= init;
else
case mode is
when init =>
--
-- Check if need to change to next
-- nested state mahcine
--
if (init_or_captured = '1') then
mode <= eval;
else
mode <= init;
end if;
when eval =>
--
-- End EVAL LOGIC nested state mahcine
--
if (init_or_captured = '0') then
mode <= eval;
else
mode <= init;
end if;
end case;
end if;
end if;
end process;
init_state_machine:
process (clk, RESET,mode,init_state) is
begin
if (rising_edge(clk)) then
if (mode = init) then
if RESET ='1' then
--TODO reset logic
init_state <= begin_init;
init_done <= '0';
else
case init_state is
--TODO: init logic
--
-- 1.A Init Machine Start
--
when begin_init =>
-- row timings set to zero to beign
row_time <= (others => (others => '0'));
init_vals(0)(FU_OUTPUT_WIDTH_NB -1 downto 0) <= Capture_vals;
if (start = '1') then
init_state <= compare;
else
init_state <= begin_init;
end if;
when compare =>
--wait one more clk cycle to get changed values
init_vals(1)(FU_OUTPUT_WIDTH_NB -1 downto 0) <= Capture_vals;
has_been_timed <= (others => '0');
init_state <= done;
when done =>
init_done <= '1';
end case;
end if;
end if;
end if;
end process;
--ready <= '1' ;
--all_timings_done <= '1';
--row_timings <= (others => (others => '1'));
--glitches <= (others => '1');
a <= '0';
end beh;
Here are the contents of DataTypes.pkg
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
package DataTypes_pkg is
constant PHASE_SHIFT_LEN_NB: integer := 11;
constant PHASE_SHIFT_RANGE: integer := 1120;
constant PHASE_SHIFT_ZEROPHASE: integer := 0;
constant FU_INPUT_WIDTH_NB: integer := 3;
constant FU_OUTPUT_WIDTH_LB: integer := 1;
constant FU_OUTPUT_WIDTH_NB: integer := 2;
constant PHASE_LOWER_BOUND: integer := 150;
constant PHASE_UPPER_BOUND: integer := 1100;
subtype InRowType is std_logic_vector(FU_INPUT_WIDTH_NB-1 downto 0);
subtype OutRowType is std_logic_vector(FU_OUTPUT_WIDTH_NB-1 downto 0);
subtype PhaseType is unsigned(PHASE_SHIFT_LEN_NB-1 downto 0);
type RowResultsType is array(FU_OUTPUT_WIDTH_NB-1 downto 0) of PhaseType;
subtype row_index_type is integer range 0 to FU_OUTPUT_WIDTH_NB - 1;
end DataTypes_pkg;
type init_vals_declare is array (0 downto 1) of std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0);
Should be
type init_vals_declare is array (0 to 1) of std_logic_vector (FU_OUTPUT_WIDTH_NB -1 downto 0);
Vivado will not tell you that the other way is wrong.