I am trying to create a small package of gates and other components for a VHDL project. I have created my package and am instantiating a component from it in my test bench, but I am receiving this compiler error:
ERROR: [VRFC 10-1412] syntax error near entity [/home/< redacted name >/Documents/school/ECE581/projects/project1/project_1/project_1.srcs/sources_1/new/components.vhdl:23]
The Question
What is the cause of my syntax error, and how do I resolve it?
Package Code
package p1_components is
component cNAND
port ( inA, inB : in bit;
output : out bit);
end component;
end p1_components;
package body p1_components is
--------------------------------------------------------------------------
-- NAND implementation
--------------------------------------------------------------------------
entity cNAND is -- *** line 23 - error is reported here ***
port ( inA, inB : in bit;
output : out bit);
end cNAND;
architecture def of cNAND is
begin
def_proc : process(inA, inB)
begin
if (inA and inB) then
output <= transport '0' after 5 ns;
else
output <= transport '1' after 5 ns;
end if;
end def_proc;
end def;
end p1_components;
Debugging Efforts
I have been referencing some standard library code here and here to ensure my declarations and syntax are correct, and as far as I can tell, they are. I have also referenced a couple of other online resources, and I can't find any issue with my package, component, and entity declarations.
Other Notes
NAND, which in a real-world design would make my implementations redundant. But the project I'm working on is for school, and there is a requirement that we roll our own NAND implementation for this portion of the project.Normally I don't put an entity inside a package but outside. Try this:
package p1_components is
component cNAND
port ( inA, inB : in bit;
output : out bit);
end component;
end p1_components;
package body p1_components is
end p1_components;
--------------------------------------------------------------------------
-- NAND implementation
--------------------------------------------------------------------------
entity cNAND is
port ( inA, inB : in bit;
output : out bit);
end cNAND;
architecture def of cNAND is
begin
def_proc : process(inA, inB)
begin
if (inA = '1' and inB = '1') then
output <= transport '0' after 5 ns;
else
output <= transport '1' after 5 ns;
end if;
end process def_proc;
end def;