I am trying to make a DNA reader module using VHDL processes for Spartan-S6 series FPGA. The problem is that my code couldn't be synthesized. It works on simulation but in synthesizing it just stucks. I also googled about unsynthesizable VHDL processes but I think that I am doing it right and it must be synthesized well. Here is my process code:
FSMOutputController:process(state,readDnaCmd)
variable clkCounter :unsigned(7 downto 0) := "00000000";
begin
case state is
when zeroState =>
if readDnaCmd = '1' then
DNA_Read <= '1';
SR_read <= '0';
else
SR_read <= '1';
end if;
when initState =>
DNA_Read <= '0';
SR_read <= '1';
SR_clk <= DNA_CLK_temp;
DNA_Shift <= '1';
when endReadState =>
DNA_shift <= '0';
SR_read <= '0';
when readState =>
clkCounter := clkCounter + 1;
--clkCounter2 <= clkCounter2 + X"01";
SR_read <= '0';
end case;
end process FSMOutputController;
And here is a part of ISE's log when trying to synthesize :
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <testDNALock>.
Related source file is "C:\Projects\Anti clone S6\code\test1\DNATest\testDNALock.vhd".
WARNING:Xst:647 - Input <CLK_98MHz> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'DNAVerify', unconnected in block 'testDNALock', is tied to its initial value (0).
Summary:
no macro.
Unit <testDNALock> synthesized.
and it stucks just in here and doesn't go for my DNALock file containing my process.There is an other thing: when I comment out assignment lines it will be synthesized correctly:
FSMOutputController:process(state,readDnaCmd)
variable clkCounter :unsigned(7 downto 0) := "00000000";
begin
case state is
when zeroState =>
if readDnaCmd = '1' then
--DNA_Read <= '1';
--SR_read <= '0';
else
--SR_read <= '1';
end if;
when initState =>
--DNA_Read <= '0';
--SR_read <= '1';
--SR_clk <= DNA_CLK_temp;
--DNA_Shift <= '1';
when endReadState =>
-- DNA_shift <= '0';
-- SR_read <= '0';
when readState =>
clkCounter := clkCounter + 1;
--clkCounter2 <= clkCounter2 + X"01";
-- SR_read <= '0';
end case;
end process FSMOutputController;
Then the report will be:
=========================================================================
* Design Summary *
=========================================================================
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -3
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: No path found
=========================================================================
Process "Synthesize - XST" completed successfully
I'm not entirely sure if it the only thing wrong. But as a minimum stuff like DNA_CLK_Temp <= not DNA_CLK_Temp after DNA_CLK_period/2; and DNAReady <= '0' after 500 ns; can't be synthesized. This means that most of you code is optimized away, as your clock never changes.
When you are simulating the code you should have a testbench module wrapping around the unit you are testing where clocks etc. are generated, instead of doing it inside your actual module.