Getting error 9: error: genvar is missing for generate "loop" variable 'r'.
1 error(s) during elaboration.
The entire code:
module divider (dividend, divisor, quotient, remainder ) ;
input [7:0] dividend ; // eight input lines modeled as a bus
input [7:0] divisor ; // select lines bundled as a bus
output reg [7:0] quotient ;
output reg [7:0] remainder ;
reg [7:0] r;
reg [7:0] q;
assign q = 0;
for(r = dividend; r >= divisor; r = r - divisor)
assign q = q + 1;
assign remainder = r;
assign quotient = q;
endmodule
module main;
reg [7:0] dd;
assign dd = 12;
reg [7:0] dr;
assign dr = 5;
reg [7:0] q;
reg [7:0] r;
wire a = divider(dd, dr, q, r);
initial begin
$display("quotient %d", q);
$display("remainder %d",r);
end
endmodule
I'm trying to write a module to calculate quotient and remainder by repeated subtraction using behavioral modeling in verilog. This is my first verilog program and I'm having trouble fixing these errors, please point out if there are any other errors in my code.
The problem is with the for loop. You can either use generate block or always block to use it. One of the way to do is as follows :
module divider (dividend, divisor,quotient, remainder ) ;
input [7:0] dividend ; // eight input lines modeled as a bus
input [7:0] divisor ; // select lines bundled as a bus
output reg [7:0] quotient ;
output reg[7:0] remainder ;
always @(*)
begin
quotient=0;
for(remainder = dividend; remainder >= divisor; remainder = remainder - divisor)
quotient = quotient + 1;
end
endmodule
module main;
reg[7:0] dd;
reg[7:0] dr;
wire [7:0] q;
wire [7:0] r;
divider d0( .dividend(dd), .divisor(dr), .quotient(q), .remainder(r) ) ;
initial begin
dd=12;
dr=5;
end
initial begin
#20 $display("quotient %d", q);
#25 $display("remainder %d",r);
end
endmodule
Few things to note: