Verilog invalid module item error

Question

I'm writing a module to calculate quotient and remainder by repeated subtraction using behavioral modeling in verilog. I'm getting the "invalid module item" error for the following code:

module divider (dividend, divisor, quotient, remainder ) ;
    input [7:0] dividend ; // eight input lines modeled as a bus
    input [7:0] divisor ; // select lines bundled as a bus
    output reg [7:0] quotient ;
    output reg [7:0] remainder ;
    reg [7:0] r;
    reg [7:0] q;
    assign q = 0;
    for(r = dividend; r >= divisor; r = r - divisor)
        assign q = q + 1;
    assign remainder = r;
    assign quotient = q;
endmodule

module main;
    reg [7:0] dd;
    assign dd = 12;
    reg [7:0] dr;
    assign dr = 5;
    reg [7:0] q;
    reg [7:0] r;
    divider(dd, dr, q, r);
    $display("quotient %d", q);
    $display("remainder %d",r);
endmodule

This seems to be a generic error, can't figure out how to fix it. The exact error message:

23: syntax error
23: error: invalid module item.
24: syntax error
24: error: invalid module item.

Answer 1

Those error messages occur because $display statements must be in a procedural block, such as initial. In this case, a $monitor might be more useful:

module main;
    reg [7:0] dd;
    assign dd = 12;
    reg [7:0] dr;
    assign dr = 5;
    reg [7:0] q;
    reg [7:0] r;
    divider(dd, dr, q, r);
    initial begin
        $monitor("quotient: %d; remainder: %d", q, r);
    end
endmodule

Refer to the free IEEE Std 1800-2012.