My Understanding on ARM MMU is low and trying to understand how Page table is organised in ARM MMU.
Page table is created at system boot up time and can be thought of as linear one dimensional array where each entry is 4 byte long but I don't understand what is 1 MB SECTION corresponds to in Page table?
If we have three level of page table, would our first level page table(PGD) contains this 1 MB section or would it (1 MB section) be only part of third level page table (PTE)?
Also what it meant by following statement:
The start of the page table is 0x40200000, each entry is 4 bytes long and each entry corresponds to a 1MB section of memory. The first entry in the page table (0x40200000) represents what happens when you try to access memory between the range of 0x00000000 to 0x00100000, the second entry (4 bytes into the table at 0x40200004) represents the memory range 0x00100000 to 0x00200000, etc.
Therefore to find the page table associated with area of memory 0x40200000 to 0x40200000+1MB (which is the 402nd MB of memory) – you need to traverse the page table list by 402 entries – but each entry is 4 bytes long therefore you need to time this number by 4.
First off there is a table in a known location in ram using physical addresses which drive the mmu. I prefer the diagram versions of the docs not the tables.
When the mmu is enabled and there is an access from the processor, fetch, or data, read or write, some number of bits from that virtual address are extracted and added to the base address of the above mmu table. the contents of the memory location in the mmu table tell the mmu what to do with that access. Some entries that is the only access and some you have to do a second mmu table access again taking some bits from the first level access and adding those to the above mmu table base address to get the second entry.
At the end of the day you have this mmu table with a base address (which must be aligned on some boundary). bits from the virtual address from a processor access are used to index into that table. the final value from the table indicates the replacement address bits to convert virtual to physical address, plus some control bits that indicate cachable or not, and permissions and such things. They apply terminlogy to that like 1MB or whatever based ideally on the amount of ram that one entry in the table controls. But of course the 16MB feature is misleading because you need 16 1MB entries in order to use it (but if you ignore the 16mb terminology and strictly look at address bits and where they come from or go to you know from that how much ram is controlled by each mmu table entry).
so what they are saying is that for some table that someone has created at some point in time. The physical address for the location of the table is 0x40200000. the 1MB size entries (for arm I think you look at the lower two bits of the entry to figure out what type it is but I would have to look and different architectures added different features so there is not one rule that fits for all, you have to look at docs for your core) are 4 bytes or one word wide and AFAIK all the entries in the mmu table are one word wide. so they are saying that one particular entry is for the 1MB of ram in virtual address space from 0x00000000 to 0x000FFFFF and the mmu table maps it to some physical address. the next entry they are showing you could be the 1MB virtual address space 0x00100000 to 0x001FFFFF and so on.